1. Technical Field
The present invention relates to ferroelectric memories.
2. Related Art
A ferroelectric memory is characterized by nonvolatility, high-speed reading/writing and low power consumption, and is one of the strong candidates of the next generation nonvolatile memories.
One of the most popular ferroelectric memory structures is a 1T1C type structure, in which each of its memory cells is composed of a transistor and a ferroelectric capacitor. The 1T1C type ferroelectric memory is characterized in that a common reference memory cell is separately provided for a plurality of memory cells, and a read-out signal for each of the memory cells and a reference signal for the reference memory cell are compared with each other at the time of read-out operation. However, the 1T1C type structure has a drawback in that deterioration of the characteristic of the reference memory cell and differences in the characteristic of the memory cells would cause read-exit errors. A method to address such a problem has been adopted, which uses a 2T2C type structure in which one of adjacent two memory cells is used as a memory cell for storing a read-out signal and the other is used as a reference memory cell for storing a reference signal. However, the 2T2C structure needs reference memory cells in the same number as that of memory cells, and therefore a reduction in area of a ferroelectric memory and a higher level of integration are difficult.
In order to solve the problem of deterioration of reference memory cells in 1T1C type ferroelectric memories, attempts have been made to obtain two signals, a read-out signal and a reference signal for the same memory cell. For example, according to Japanese Laid-open Patent Application JP-A-9-180467, a read-out signal and a “1” read-out signal are compared. As a comparing method, a potential difference detected by a sense amplifier caused by a “1” read-out signal after a read-out signal is compared with a reference voltage. Also, in Japanese Laid-open Patent Application JP-A-11-191295, a read-out signal and a “0” read-out signal are compared. As a comparing method, the two signals are inputted in independent differential sense amplifiers, respectively, and compared with each other. Further, in Japanese Laid-open Patent Application JP-A-2001-180286, a read-out signal and a “1” read-out signal are compared, like the method described in Japanese Laid-open Patent Application JP-A-9-180467. As a comparing method, the read-out signals are buffered in independent capacitors, respectively, and then compared by using an evaluator.